1. Field of the Invention
The invention relates to an apparatus for generating pseudo-noise codes, and in particular to an apparatus for generating pseudo-noise codes adapted for advancing or retarding 1 pseudo-noise chip generated therefrom within one clock cycle in a radio communication network based on code division multiple access (CDMA), and a method for generating pseudo-noise codes by using the pseudo-noise code generating apparatus.
2. Description of the Related Art
In a radio communication network based on the code division multiple access (hereinafter will be referred to CDMA), a pseudo-noise or pseudorandom noise generator is generally applied to a receiving or transmitting end of a communication apparatus. A pseudo noise code generator applied to the receiving end performs user discrimination, time and phase locking and decoding on signals received from the receiving end by generating pseudo-noise (hereinafter will be referred to PN) sequence.
In IS-95 as the international standard of the CDMA communication system, a Long PN code generator for (242-1) beat length and a short PN code generator for 215 are currently recommended. Herein, the short PN code generator generates short PN code lines of 215 beat length in respect to each of an in-phase (hereinafter will referred to I) channel and a quadrature-phase (hereinafter will be referred to Q) channel.
Again, a typical PN code generator has length of (2n-1). Therefore, the foregoing PN code generator of the IS-95 standard can be referred as a typical PN code generator. However, the short PN code generator is modified from the typical PN code generator by inserting “0” beat output to generate 2n beat length.
The PIN codes generated from these pseudo noise code generators are generated by a Linear sequence shift register (hereinafter will be referred to LSSR) composed of n number of flip-flops of shift registers. In particular, the pseudo noise code generators are applied so that a searcher of a base station receiver or terminal receiver can rapidly acquire pilot signals included in the received signals and a finger of the receiver can track the PN codes included in the received signals. Here, the PN codes are generated by the pseudo noise code generator to find PN codes included in the received signals in the receiver of the base station or terminal, and offsets of the PN codes are intentionally retarded or advanced to perform operations for acquiring pilot signals or finding the PN codes.
FIG. 1 is a block diagram for showing the configuration of a PN code generator of the prior art, wherein 4 stage LSSR 1 to 4 is used.
Before explaining the apparatus shown in FIG. 1, it should be understood that N times clock of the PN chip rate is used for a system clock. Namely, the system clock is “chip rate × N.” The number of clocks applied to the LSSR 1 to 4 of FIG. 1 is adjusted through a clock enable according to the system clock, and accordingly the PN code generator shown in FIG. 1 is normally operated and one PN chip advance or one PN chip retard is performed.
In FIG. 1, when the PN code generator composed of an exclusive OR(EOR) gate 5 and 4 stage LSSRs 1 to 4 is normally operated, the clock enable is enabled with one system clock for N number of system clocks. In this way, one system clock is applied to the LSSRs 1 to 4 during one PN chip time period.
However, the PN code lines, after generated according to the normal operation of the PN code generator, are intentionally retarded or advanced for one PN chip so as to be used for code acquisition or code tracking.
One next PN chip retard means that the state of the LSSR 1 to 4 is repeated for one PN chip time period, in which zero system clock is applied to the LSSR 1 to 4 during one PN chip time period or N number of system clocks by adjusting the clock enable.
One next PN chip advance means that the state of the LSSR 1 to 4 bypasses the next state to transit into the second state, wherein 2 system clocks are applied to LSSR 1 to 4 during one chip time period or N number of system clocks. Therefore, the conventional PN code generating methods have a problem that a system clock at least two times of the PN chip speed is required for one PN chip advance.
In other words, in the communication atmosphere from now on, requirements about functions of a modem of each communication equipment including the base station or terminal are getting more various. Therefore, structure of a modem(MSM) is being more complex and number of subscribers on the radio communication network is gradually increasing also. Accordingly, a pseudo noise code generator is required which can carry out one PN chip retard or advance within the minimum system clocks available in this communication atmosphere.